library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
--library work;
--   use work.UART_Def.all;

entity DMXuart_2 is
  port (
     SysClk   		: in  	Std_Logic;  -- System Clock
     Reset    		: in  	Std_Logic;  -- Reset input
     RxD      		: in  	Std_Logic;
   DataRdy		    : out 	Std_Logic;	-- Externalised Drdy signal
   DMXAddr		    : in     Unsigned(7 downto 0);
   --DataOut  		: out 	Std_Logic_Vector(7 downto 0); -- 
	 BreakDetected	: out 	Std_Logic;
	 
	 Channel0		: out   Std_Logic_Vector(7 downto 0); 
	 Channel1		: out   Std_Logic_Vector(7 downto 0); 
	 Channel2		: out   Std_Logic_Vector(7 downto 0); 
	 Channel3		: out   Std_Logic_Vector(7 downto 0);
	 Channel4		: out   Std_Logic_Vector(7 downto 0); 
	 Channel5		: out   Std_Logic_Vector(7 downto 0);
	 Channel6		: out   Std_Logic_Vector(7 downto 0);
	 Channel7		: out   Std_Logic_Vector(7 downto 0);
	 Channel8		: out   Std_Logic_Vector(7 downto 0);
	 Channel9		: out   Std_Logic_Vector(7 downto 0);
	 Channel10		: out   Std_Logic_Vector(7 downto 0);
	 Channel11		: out   Std_Logic_Vector(7 downto 0);
	 Channel12		: out   Std_Logic_Vector(7 downto 0);
	 Channel13		: out   Std_Logic_Vector(7 downto 0);
	 Channel14		: out   Std_Logic_Vector(7 downto 0);
	 Channel15		: out   Std_Logic_Vector(7 downto 0);
	 Channel16		: out   Std_Logic_Vector(7 downto 0);
	 Channel17		: out   Std_Logic_Vector(7 downto 0);
	 Channel18		: out   Std_Logic_Vector(7 downto 0);
	 Channel19		: out   Std_Logic_Vector(7 downto 0);
	 Channel20		: out   Std_Logic_Vector(7 downto 0);
	 Channel21		: out   Std_Logic_Vector(7 downto 0);
	 Channel22		: out   Std_Logic_Vector(7 downto 0);
	 Channel23		: out   Std_Logic_Vector(7 downto 0);
	 Channel24		: out   Std_Logic_Vector(7 downto 0);
	 Channel25		: out   Std_Logic_Vector(7 downto 0);
	 Channel26		: out   Std_Logic_Vector(7 downto 0);
	 Channel27		: out   Std_Logic_Vector(7 downto 0);
	 Channel28		: out   Std_Logic_Vector(7 downto 0);
	 Channel29		: out   Std_Logic_Vector(7 downto 0);
	 Channel30		: out   Std_Logic_Vector(7 downto 0);
	 Channel31		: out   Std_Logic_Vector(7 downto 0);
	 Channel32		: out   Std_Logic_Vector(7 downto 0);
	 Channel33		: out   Std_Logic_Vector(7 downto 0);
	 Channel34		: out   Std_Logic_Vector(7 downto 0);
	 Channel35		: out   Std_Logic_Vector(7 downto 0);
	 Channel36		: out   Std_Logic_Vector(7 downto 0); 
	 Channel37		: out   Std_Logic_Vector(7 downto 0); 
	 Channel38		: out   Std_Logic_Vector(7 downto 0); 
	 Channel39		: out   Std_Logic_Vector(7 downto 0);
	 Channel40		: out   Std_Logic_Vector(7 downto 0); 
	 Channel41		: out   Std_Logic_Vector(7 downto 0);
	 Channel42		: out   Std_Logic_Vector(7 downto 0);
	 Channel43		: out   Std_Logic_Vector(7 downto 0);
	 Channel44		: out   Std_Logic_Vector(7 downto 0);
	 Channel45		: out   Std_Logic_Vector(7 downto 0);
	 Channel46		: out   Std_Logic_Vector(7 downto 0);
	 Channel47		: out   Std_Logic_Vector(7 downto 0);
	 Channel48		: out   Std_Logic_Vector(7 downto 0);
	 Channel49		: out   Std_Logic_Vector(7 downto 0);
	 Channel50		: out   Std_Logic_Vector(7 downto 0);
	 Channel51		: out   Std_Logic_Vector(7 downto 0);
	 Channel52		: out   Std_Logic_Vector(7 downto 0);
	 Channel53		: out   Std_Logic_Vector(7 downto 0);
	 Channel54		: out   Std_Logic_Vector(7 downto 0);
	 Channel55		: out   Std_Logic_Vector(7 downto 0);
	 Channel56		: out   Std_Logic_Vector(7 downto 0);
	 Channel57		: out   Std_Logic_Vector(7 downto 0);
	 Channel58		: out   Std_Logic_Vector(7 downto 0);
	 Channel59		: out   Std_Logic_Vector(7 downto 0);
	 Channel60		: out   Std_Logic_Vector(7 downto 0);
	 Channel61		: out   Std_Logic_Vector(7 downto 0);
	 Channel62	    : out   Std_Logic_Vector(7 downto 0);
	 Channel63		: out   Std_Logic_Vector(7 downto 0);
	 Channel64		: out   Std_Logic_Vector(7 downto 0);
	 Channel65		: out   Std_Logic_Vector(7 downto 0);
	 Channel66		: out   Std_Logic_Vector(7 downto 0);
	 Channel67		: out   Std_Logic_Vector(7 downto 0);
	 Channel68		: out   Std_Logic_Vector(7 downto 0);
	 Channel69		: out   Std_Logic_Vector(7 downto 0);
	 Channel70		: out   Std_Logic_Vector(7 downto 0);
	 Channel71		: out   Std_Logic_Vector(7 downto 0);
     Channel72		: out   Std_Logic_Vector(7 downto 0); 
	 Channel73		: out   Std_Logic_Vector(7 downto 0); 
	 Channel74		: out   Std_Logic_Vector(7 downto 0); 
	 Channel75		: out   Std_Logic_Vector(7 downto 0);
	 Channel76		: out   Std_Logic_Vector(7 downto 0); 
	 Channel77		: out   Std_Logic_Vector(7 downto 0);
	 Channel78		: out   Std_Logic_Vector(7 downto 0);
	 Channel79		: out   Std_Logic_Vector(7 downto 0);
	 Channel80		: out   Std_Logic_Vector(7 downto 0);
	 Channel81		: out   Std_Logic_Vector(7 downto 0);
	 Channel82		: out   Std_Logic_Vector(7 downto 0);
	 Channel83		: out   Std_Logic_Vector(7 downto 0);
	 Channel84		: out   Std_Logic_Vector(7 downto 0);
	 Channel85		: out   Std_Logic_Vector(7 downto 0);
	 Channel86		: out   Std_Logic_Vector(7 downto 0);
	 Channel87		: out   Std_Logic_Vector(7 downto 0);
	 Channel88		: out   Std_Logic_Vector(7 downto 0);
	 Channel89		: out   Std_Logic_Vector(7 downto 0);
	 Channel90		: out   Std_Logic_Vector(7 downto 0);
	 Channel91		: out   Std_Logic_Vector(7 downto 0);
	 Channel92		: out   Std_Logic_Vector(7 downto 0);
	 Channel93		: out   Std_Logic_Vector(7 downto 0);
	 Channel94		: out   Std_Logic_Vector(7 downto 0);
	 Channel95		: out   Std_Logic_Vector(7 downto 0);
	 Channel96		: out   Std_Logic_Vector(7 downto 0);
	 Channel97		: out   Std_Logic_Vector(7 downto 0);
	 Channel98		: out   Std_Logic_Vector(7 downto 0);
	 Channel99		: out   Std_Logic_Vector(7 downto 0));
	


	
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for miniUART Controller Unit
-------------------------------------------------------------------------------
architecture uart of DMXuart_2 is
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
	type STATE_TYPE is (WAITFORBREAK, WAITFORSTARTBYTE, WAITFORDMXADDR, WAITFORDMXADDREND);
	signal State 		: STATE_TYPE := WAITFORBREAK;
	signal RxData1		: Std_Logic_Vector(7 downto 0) := "00000000"; -- 
	signal RxData2 		: Std_Logic_Vector(7 downto 0) := "00000101"; 
    signal RxData3 		: Std_Logic_Vector(7 downto 0) := "00000111"; -- 
	signal RxData4 		: Std_Logic_Vector(7 downto 0) := "00001001";   
    signal RxData5 		: Std_Logic_Vector(7 downto 0) := "00001110"; -- 
	signal RxData6 		: Std_Logic_Vector(7 downto 0) := "00010001"; 
    signal RxData7 		: Std_Logic_Vector(7 downto 0) := "00010011"; -- 
	signal RxData8 		: Std_Logic_Vector(7 downto 0) := "00010111"; 
    signal RxData9 		: Std_Logic_Vector(7 downto 0) := "00011001"; -- 
	signal RxData10 	: Std_Logic_Vector(7 downto 0) := "00101000"; 
    signal RxData11 	: Std_Logic_Vector(7 downto 0) := "00101101"; -- 
	signal RxData12 	: Std_Logic_Vector(7 downto 0) := "00110001"; 
    signal RxData13 	: Std_Logic_Vector(7 downto 0) := "00110100"; -- 
	signal RxData14 	: Std_Logic_Vector(7 downto 0) := "00110111"; 
    signal RxData15 	: Std_Logic_Vector(7 downto 0) := "00111111"; -- 
	signal RxData16 	: Std_Logic_Vector(7 downto 0) := "01000011"; 
    signal RxData17 	: Std_Logic_Vector(7 downto 0) := "01000100"; -- 
	signal RxData18 	: Std_Logic_Vector(7 downto 0) := "01010100"; 
    signal RxData19 	: Std_Logic_Vector(7 downto 0) := "01010101"; -- 
	signal RxData20     : Std_Logic_Vector(7 downto 0) := "01011001"; 
    signal RxData21 	: Std_Logic_Vector(7 downto 0) := "01101001"; -- 
	signal RxData22 	: Std_Logic_Vector(7 downto 0) := "01101101"; 
    signal RxData23 	: Std_Logic_Vector(7 downto 0) := "01110000"; -- 
	signal RxData24 	: Std_Logic_Vector(7 downto 0) := "01110101"; 
    signal RxData25 	: Std_Logic_Vector(7 downto 0) := "01111110"; -- 
	signal RxData26 	: Std_Logic_Vector(7 downto 0) := "01101101"; 
    signal RxData27		: Std_Logic_Vector(7 downto 0) := "01110110"; -- 
	signal RxData28 	: Std_Logic_Vector(7 downto 0) := "01111011"; 
    signal RxData29 	: Std_Logic_Vector(7 downto 0) := "01000001"; -- 
	signal RxData30 	: Std_Logic_Vector(7 downto 0) := "10000100"; 
    signal RxData31 	: Std_Logic_Vector(7 downto 0) := "10001010"; -- 
	signal RxData32 	: Std_Logic_Vector(7 downto 0) := "10001101"; 
    signal RxData33 	: Std_Logic_Vector(7 downto 0) := "10010010"; -- 
	signal RxData34 	: Std_Logic_Vector(7 downto 0) := "11111001"; 
    signal RxData35 	: Std_Logic_Vector(7 downto 0) := "11111101"; -- 
	signal RxData36 	: Std_Logic_Vector(7 downto 0) := "10010111"; 
	signal RxData37		: Std_Logic_Vector(7 downto 0) := "10011101"; -- 
	signal RxData38		: Std_Logic_Vector(7 downto 0) := "10100010"; 
    signal RxData39 	: Std_Logic_Vector(7 downto 0) := "10101101"; -- 
	signal RxData40 	: Std_Logic_Vector(7 downto 0) := "10110011";   
    signal RxData41 	: Std_Logic_Vector(7 downto 0) := "10110110"; -- 
	signal RxData42 	: Std_Logic_Vector(7 downto 0) := "10111101";                      
    signal RxData43 	: Std_Logic_Vector(7 downto 0) := "10111111"; -- 
	signal RxData44 	: Std_Logic_Vector(7 downto 0) := "11001100"; 
    signal RxData45 	: Std_Logic_Vector(7 downto 0) := "11010001"; -- 
	signal RxData46 	: Std_Logic_Vector(7 downto 0) := "11010011"; 
    signal RxData47 	: Std_Logic_Vector(7 downto 0) := "11011010"; -- 
	signal RxData48 	: Std_Logic_Vector(7 downto 0) := "11011011"; 
    signal RxData49 	: Std_Logic_Vector(7 downto 0) := "11011110"; -- 
	signal RxData50 	: Std_Logic_Vector(7 downto 0) := "11100101"; 
    signal RxData51 	: Std_Logic_Vector(7 downto 0) := "11111111"; -- 
	signal RxData52 	: Std_Logic_Vector(7 downto 0) := "11101000"; 
    signal RxData53 	: Std_Logic_Vector(7 downto 0) := "11101100"; -- 
	signal RxData54 	: Std_Logic_Vector(7 downto 0) := "11101111"; 
    signal RxData55 	: Std_Logic_Vector(7 downto 0) := "11110001"; -- 
	signal RxData56     : Std_Logic_Vector(7 downto 0) := "11110011"; 
    signal RxData57 	: Std_Logic_Vector(7 downto 0) := "11110111"; -- 
	signal RxData58 	: Std_Logic_Vector(7 downto 0) := "11111001"; 
    signal RxData59 	: Std_Logic_Vector(7 downto 0) := "11111011"; -- 
	signal RxData60 	: Std_Logic_Vector(7 downto 0) := "11010010"; 
    signal RxData61 	: Std_Logic_Vector(7 downto 0) := "11011001"; -- 
	signal RxData62 	: Std_Logic_Vector(7 downto 0) := "11101010"; 
    signal RxData63	    : Std_Logic_Vector(7 downto 0) := "11100010"; -- 
	signal RxData64 	: Std_Logic_Vector(7 downto 0) := "11110000"; 
    signal RxData65 	: Std_Logic_Vector(7 downto 0) := "11110110"; -- 
	signal RxData66 	: Std_Logic_Vector(7 downto 0) := "11111000"; 
    signal RxData67 	: Std_Logic_Vector(7 downto 0) := "11111100"; -- 
	signal RxData68 	: Std_Logic_Vector(7 downto 0) := "10101110"; 
    signal RxData69 	: Std_Logic_Vector(7 downto 0) := "10110000"; -- 
	signal RxData70 	: Std_Logic_Vector(7 downto 0) := "10100000"; 
    signal RxData71 	: Std_Logic_Vector(7 downto 0) := "10011010"; -- 
	signal RxData72	    : Std_Logic_Vector(7 downto 0) := "10011100"; 
    signal RxData73		: Std_Logic_Vector(7 downto 0) := "10011001"; -- 
	signal RxData74 	: Std_Logic_Vector(7 downto 0) := "10001111"; 
    signal RxData75 	: Std_Logic_Vector(7 downto 0) := "01100011"; -- 
	signal RxData76 	: Std_Logic_Vector(7 downto 0) := "10000000";   
    signal RxData77 	: Std_Logic_Vector(7 downto 0) := "10001001"; -- 
	signal RxData78		: Std_Logic_Vector(7 downto 0) := "10010100"; 
    signal RxData79		: Std_Logic_Vector(7 downto 0) := "00110110"; -- 
	signal RxData80 	: Std_Logic_Vector(7 downto 0) := "00111101"; 
    signal RxData81 	: Std_Logic_Vector(7 downto 0) := "00010100"; -- 
	signal RxData82 	: Std_Logic_Vector(7 downto 0) := "00011010"; 
    signal RxData83 	: Std_Logic_Vector(7 downto 0) := "00010011"; -- 
	signal RxData84 	: Std_Logic_Vector(7 downto 0) := "10001011"; 
    signal RxData85 	: Std_Logic_Vector(7 downto 0) := "10010000"; -- 
	signal RxData86	    : Std_Logic_Vector(7 downto 0) := "01010001"; 
    signal RxData87 	: Std_Logic_Vector(7 downto 0) := "01011011"; -- 
	signal RxData88 	: Std_Logic_Vector(7 downto 0) := "01100000"; 
    signal RxData89 	: Std_Logic_Vector(7 downto 0) := "01111101"; -- 
	signal RxData90	    : Std_Logic_Vector(7 downto 0) := "10001000"; 
    signal RxData91 	: Std_Logic_Vector(7 downto 0) := "10000010"; -- 
	signal RxData92     : Std_Logic_Vector(7 downto 0) := "01111000"; 
    signal RxData93 	: Std_Logic_Vector(7 downto 0) := "01101110"; -- 
	signal RxData94 	: Std_Logic_Vector(7 downto 0) := "10111001"; 
    signal RxData95 	: Std_Logic_Vector(7 downto 0) := "11000100"; -- 
	signal RxData96 	: Std_Logic_Vector(7 downto 0) := "01100100"; 
    signal RxData97	    : Std_Logic_Vector(7 downto 0) := "01111010"; -- 
	signal RxData98 	: Std_Logic_Vector(7 downto 0) := "11011000"; 
    signal RxData99		: Std_Logic_Vector(7 downto 0) := "01101111"; -- 
	signal RxData100	: Std_Logic_Vector(7 downto 0) := "11100110"; 
	
	signal BREAK   		: Std_Logic := '0';  -- Frame error
	--signal BitCnt 		: Std_Logic_Vector(4 downto 0);--
	signal BitStart		: Std_Logic := '0';
--	shared variable DMXaddress	: Integer range 0 to 255 :=0;
	shared variable ByteNumber      : Integer range 0 to 255 :=0;
	constant CntOne                       : Unsigned(3 downto 0):="0001";
	--signal ByteAddr		: Unsigned(3 downto 0);  -- samples on one bit counter--
  -----------------------------------------------------------------------------
  -- Receive Unit
  -----------------------------------------------------------------------------
  component RxUnit is
  port (
     Clk    	: in  Std_Logic;  -- Clock signal
     Reset  	: in  Std_Logic;  -- Reset input
     RxD    	: in  Std_Logic;  -- RS-232 data input
     BREAK  	: out Std_Logic;  -- Status signal
     DataIn1  	: out Std_Logic_Vector(7 downto 0);
     DataIn2 	: out Std_Logic_Vector(7 downto 0);
     DataIn3  	: out Std_Logic_Vector(7 downto 0);
     DataIn4 	: out Std_Logic_Vector(7 downto 0);
     DataIn5  	: out Std_Logic_Vector(7 downto 0);
     DataIn6	: out Std_Logic_Vector(7 downto 0);
     DataIn7  	: out Std_Logic_Vector(7 downto 0);
     DataIn8	: out Std_Logic_Vector(7 downto 0);
     DataIn9  	: out Std_Logic_Vector(7 downto 0);
     DataIn10 	: out Std_Logic_Vector(7 downto 0);
     DataIn11  	: out Std_Logic_Vector(7 downto 0);
     DataIn12 	: out Std_Logic_Vector(7 downto 0);
     DataIn13  	: out Std_Logic_Vector(7 downto 0);
     DataIn14 	: out Std_Logic_Vector(7 downto 0);
     DataIn15  	: out Std_Logic_Vector(7 downto 0);
     DataIn16 	: out Std_Logic_Vector(7 downto 0);
     DataIn17  	: out Std_Logic_Vector(7 downto 0);
     DataIn18 	: out Std_Logic_Vector(7 downto 0);
     DataIn19  	: out Std_Logic_Vector(7 downto 0);
     DataIn20 	: out Std_Logic_Vector(7 downto 0);
     DataIn21  	: out Std_Logic_Vector(7 downto 0);
     DataIn22 	: out Std_Logic_Vector(7 downto 0);
     DataIn23 	: out Std_Logic_Vector(7 downto 0);
     DataIn24 	: out Std_Logic_Vector(7 downto 0);
     DataIn25 	: out Std_Logic_Vector(7 downto 0);
     DataIn26 	: out Std_Logic_Vector(7 downto 0);
     DataIn27  	: out Std_Logic_Vector(7 downto 0);
     DataIn28 	: out Std_Logic_Vector(7 downto 0);
     DataIn29  	: out Std_Logic_Vector(7 downto 0);
     DataIn30 	: out Std_Logic_Vector(7 downto 0);
     DataIn31 	: out Std_Logic_Vector(7 downto 0);
     DataIn32 	: out Std_Logic_Vector(7 downto 0);
     DataIn33  	: out Std_Logic_Vector(7 downto 0);
     DataIn34 	: out Std_Logic_Vector(7 downto 0);
     DataIn35  	: out Std_Logic_Vector(7 downto 0);
     DataIn36 	: out Std_Logic_Vector(7 downto 0);
     DataIn37  	: out Std_Logic_Vector(7 downto 0);
     DataIn38 	: out Std_Logic_Vector(7 downto 0);
     DataIn39  	: out Std_Logic_Vector(7 downto 0);
     DataIn40 	: out Std_Logic_Vector(7 downto 0);
     DataIn41  	: out Std_Logic_Vector(7 downto 0);
     DataIn42	: out Std_Logic_Vector(7 downto 0);
     DataIn43  	: out Std_Logic_Vector(7 downto 0);
     DataIn44	: out Std_Logic_Vector(7 downto 0);
     DataIn45  	: out Std_Logic_Vector(7 downto 0);
     DataIn46 	: out Std_Logic_Vector(7 downto 0);
     DataIn47  	: out Std_Logic_Vector(7 downto 0);
     DataIn48 	: out Std_Logic_Vector(7 downto 0);
     DataIn49  	: out Std_Logic_Vector(7 downto 0);
     DataIn50 	: out Std_Logic_Vector(7 downto 0);
     DataIn51  	: out Std_Logic_Vector(7 downto 0);
     DataIn52 	: out Std_Logic_Vector(7 downto 0);
     DataIn53  	: out Std_Logic_Vector(7 downto 0);
     DataIn54 	: out Std_Logic_Vector(7 downto 0);
     DataIn55  	: out Std_Logic_Vector(7 downto 0);
     DataIn56 	: out Std_Logic_Vector(7 downto 0);
     DataIn57 	: out Std_Logic_Vector(7 downto 0);
     DataIn58 	: out Std_Logic_Vector(7 downto 0);
     DataIn59 	: out Std_Logic_Vector(7 downto 0);
     DataIn60 	: out Std_Logic_Vector(7 downto 0);
     DataIn61 	: out Std_Logic_Vector(7 downto 0);
     DataIn62 	: out Std_Logic_Vector(7 downto 0);
     DataIn63  	: out Std_Logic_Vector(7 downto 0);
     DataIn64 	: out Std_Logic_Vector(7 downto 0);
     DataIn65  	: out Std_Logic_Vector(7 downto 0);
     DataIn66 	: out Std_Logic_Vector(7 downto 0);
     DataIn67 	: out Std_Logic_Vector(7 downto 0);
     DataIn68 	: out Std_Logic_Vector(7 downto 0);
     DataIn69  	: out Std_Logic_Vector(7 downto 0);
     DataIn70 	: out Std_Logic_Vector(7 downto 0);
     DataIn71  	: out Std_Logic_Vector(7 downto 0);
     DataIn72 	: out Std_Logic_Vector(7 downto 0);
     DataIn73  	: out Std_Logic_Vector(7 downto 0);
     DataIn74 	: out Std_Logic_Vector(7 downto 0);
     DataIn75  	: out Std_Logic_Vector(7 downto 0);
     DataIn76 	: out Std_Logic_Vector(7 downto 0);
     DataIn77  	: out Std_Logic_Vector(7 downto 0);
     DataIn78	: out Std_Logic_Vector(7 downto 0);
     DataIn79  	: out Std_Logic_Vector(7 downto 0);
     DataIn80	: out Std_Logic_Vector(7 downto 0);
     DataIn81  	: out Std_Logic_Vector(7 downto 0);
     DataIn82 	: out Std_Logic_Vector(7 downto 0);
     DataIn83  	: out Std_Logic_Vector(7 downto 0);
     DataIn84 	: out Std_Logic_Vector(7 downto 0);
     DataIn85  	: out Std_Logic_Vector(7 downto 0);
     DataIn86 	: out Std_Logic_Vector(7 downto 0);
     DataIn87  	: out Std_Logic_Vector(7 downto 0);
     DataIn88 	: out Std_Logic_Vector(7 downto 0);
     DataIn89  	: out Std_Logic_Vector(7 downto 0);
     DataIn90 	: out Std_Logic_Vector(7 downto 0);
     DataIn91  	: out Std_Logic_Vector(7 downto 0);
     DataIn92 	: out Std_Logic_Vector(7 downto 0);
     DataIn93  	: out Std_Logic_Vector(7 downto 0);
     DataIn94 	: out Std_Logic_Vector(7 downto 0);
     DataIn95 	: out Std_Logic_Vector(7 downto 0);
     DataIn96 	: out Std_Logic_Vector(7 downto 0);
     DataIn97 	: out Std_Logic_Vector(7 downto 0);
     DataIn98 	: out Std_Logic_Vector(7 downto 0);
     DataIn99  	: out Std_Logic_Vector(7 downto 0);
     DataIn100 	: out Std_Logic_Vector(7 downto 0);
     BitStart	: out Std_Logic);
  end component;

begin
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
  RxDev   : RxUnit port map (SysClk,Reset,RxD,BREAK,RxData1,RxData2,RxData3,RxData4,RxData5,RxData6,RxData7,RxData8,RxData9,RxData10,RxData11,RxData12,
                                             RxData13,RxData14,RxData15,RxData16,RxData17,RxData18,RxData19,RxData20,RxData21,RxData22,RxData23,
                                             RxData24,RxData25,RxData26,RxData27,RxData28,RxData29,RxData30,RxData31,RxData32,RxData33,RxData34,RxData35,RxData36,RxData37,RxData38,RxData39,RxData40,RxData41,RxData42,RxData43,RxData44,RxData45,RxData46,RxData47,RxData48,
                                             RxData49,RxData50,RxData51,RxData52,RxData53,RxData54,RxData55,RxData56,RxData57,RxData58,RxData59,RxData60,RxData61,RxData62,
                                             RxData63,RxData64,RxData65,RxData66,RxData67,RxData68,RxData69,RxData70,RxData71,RxData72,RxData73,RxData74,RxData75,RxData76,
                                             RxData77,RxData78,RxData79,RxData80,RxData81,RxData82,RxData83,RxData84,RxData85,RxData86,RxData87,
                                             RxData88,RxData89,RxData90,RxData91,RxData92,RxData93,RxData94,RxData95,RxData96,RxData97,RxData98,RxData99,RxData100,BitStart);
  -----------------------------------------------------------------------------


  -----------------------------------------------------------------------------
  -- Background processes
  -----------------------------------------------------------------------------

BreakDetected	<= 	BREAK;

  -----------------------------------------------------------------------------
  -- Combinational section
  -----------------------------------------------------------------------------
	process(SysClk, DMXAddr, State, BitStart)
	begin
		
--		DMXaddress 	:= To_Integer(DMXAddr);
		--if State = WAITFORDMXADDREND then
			DataRdy	<= 	BitStart;
		--else
		--	DataRdy <= '0';	
		--end if;
  	end process;



  -----------------------------------------------------------------------------
  -- State machine
  -----------------------------------------------------------------------------
	process(SysClk,State,BREAK,BitStart,Reset,RxData1,RxData2,RxData3,RxData4,RxData5,RxData6,RxData7,RxData8,RxData9,RxData10,RxData11,RxData12,
                                             RxData13,RxData14,RxData15,RxData16,RxData17,RxData18,RxData19,RxData20,RxData21,RxData22,RxData23,
                                             RxData24,RxData25,RxData26,RxData27,RxData28,RxData29,RxData30,RxData31,RxData32,RxData33,RxData34,RxData35,RxData36,RxData37,RxData38,RxData39,RxData40,RxData41,RxData42,RxData43,RxData44,RxData45,RxData46,RxData47,RxData48,
                                             RxData49,RxData50,RxData51,RxData52,RxData53,RxData54,RxData55,RxData56,RxData57,RxData58,RxData59,RxData60,RxData61,RxData62,
                                             RxData63,RxData64,RxData65,RxData66,RxData67,RxData68,RxData69,RxData70,RxData71,RxData72,RxData73,RxData74,RxData75,RxData76,
                                             RxData77,RxData78,RxData79,RxData80,RxData81,RxData82,RxData83,RxData84,RxData85,RxData86,RxData87,
                                             RxData88,RxData89,RxData90,RxData91,RxData92,RxData93,RxData94,RxData95,RxData96,RxData97,RxData98,RxData99,RxData100)
	
	
	
	
--	SysClk   		
--	Reset    		
--	RxD      		
--	DataRdy		
--	DMXAddr		
--	DataOut  		


--State		
--RxData 	
--RxData2 		
--BREAK   		
--BitStart		

   


	--variable ByteNumber : Integer range 0 to 512 :=0;
	--variable DMXaddress	: Integer range 0 to 255 :=0;
	begin
		
RxData1<=   RxData2 OR RxData3 OR RxData4 OR RxData5 OR RxData6 OR RxData7 OR RxData8 OR 
					RxData9 OR RxData10 OR RxData11 OR RxData12 OR RxData13 OR RxData14 OR RxData15 OR
					RxData16 OR RxData17 OR RxData18 OR RxData19 OR RxData20 OR RxData21 OR RxData22 OR 
					RxData23 OR RxData24 OR RxData25 OR RxData26 OR RxData27 OR RxData28 OR RxData29 OR 
					RxData30 OR RxData31 OR RxData32 OR RxData33 OR RxData34 OR RxData35 OR RxData36 OR 
					RxData37 OR RxData38 OR RxData39 OR RxData40 OR RxData41 OR RxData42 OR RxData43 OR 
					RxData44 OR RxData45 OR RxData46 OR RxData47 OR RxData48 OR RxData49 OR RxData50 OR 
					RxData51 OR RxData52 OR RxData53 OR RxData54 OR RxData55 OR RxData56 OR RxData57 OR 
					RxData58 OR RxData59 OR RxData60 OR RxData61 OR RxData62 OR RxData63 OR RxData64 OR
				   RxData65 OR RxData66 OR RxData67 OR RxData68 OR RxData69 OR RxData70 OR RxData71 OR 
					RxData72 OR RxData73 OR RxData74 OR RxData75 OR RxData76 OR RxData77 OR RxData78 OR 
				   RxData79 OR RxData80 OR RxData81 OR RxData82 OR RxData83 OR RxData84 OR RxData85 OR 
					RxData86 OR RxData87 OR RxData88 OR RxData89 OR RxData90 OR RxData91 OR RxData92 OR 
					RxData93 OR RxData94 OR RxData95 OR RxData96 OR RxData97 OR RxData98 OR RxData99 OR
					RxData100 ;
		
		
		if (Reset = '0') then
			State <= WAITFORBREAK;
		elsif (BitStart'event and BitStart = '0') then
--			DMXaddress 	:= To_Integer(DMXAddr);		
			case State is
				--======================================--
				when WAITFORBREAK =>					-- Waiting for a new BREAK signal
					if BREAK = '1' then
						State <= WAITFORSTARTBYTE;		-- Break detected, wait for 1st byte
--						DMXaddress 	:= To_Integer(DMXAddr);	---------SOHULD BE COMMENTED---------------	
						ByteNumber := 0;
					end if;

				--======================================--
				when WAITFORSTARTBYTE => 				-- Waiting for first byte (all zeros..)
--						
					if    RxData1 = "00000000" then
						State <= WAITFORDMXADDR;		-- Start byte detected
					else
						State <= WAITFORBREAK;			-- Go back to waiting for BREAK...
					end if;
				--======================================--					
				when WAITFORDMXADDR =>					-- Waiting for DMX address match	
--					if ByteNumber = DMXaddress then		-- Are we at the start address yet?---------SOHULD NOT BE COMMENTED---------------	
					if ByteNumber = To_Integer(DMXAddr) then		-- Are we at the start address yet?--------EXTRA-----------
						Channel0 <= RxData1;
						ByteNumber := 0;				-- reset the counter
						State <= WAITFORDMXADDREND;		-- yes, so now wait for all channels to be received
					else
						ByteNumber := ByteNumber + 1;	-- No, so increment the counter
						if (ByteNumber = 255) then		-- Check for overrun...
							State <= WAITFORBREAK;		-- Overflow, so go back to waiting for a BREAK signal
						end if;
					end if;
					if (BREAK = '1') then				-- Keep a check on current conditions
						State <= WAITFORSTARTBYTE;		-- Unexpected BREAK detected...
						ByteNumber := 0;				-- Abandon everything!
					end if;
				--======================================--					
				when WAITFORDMXADDREND =>
					  ByteNumber := ByteNumber + 1;		-- Increment counters
					  if ByteNumber = 100 then				-- have we received all channels?
						State <= WAITFORBREAK;			-- yes, so go back to waiting for a BREAK signal
					end if;
					case ByteNumber is
						when 1 => 
							Channel1 <= RxData2;
						when 2  =>
							Channel2 <= RxData3;
						when 3  =>
						    Channel3 <= RxData4;
                        when 4  => 
							Channel4 <= RxData5;
						when 5  => 
							Channel5 <= RxData6;
                        when 6 => 
							Channel6 <= RxData7;
						when 7  =>
							Channel7 <= RxData8;
						when 8 =>
						     Channel8 <= RxData9;
                        when 9 => 
							Channel9 <= RxData10;
						when 10  => 
							Channel10 <= RxData11;
                        when 11 => 
							Channel11 <= RxData12;
						when 12  =>
							Channel12 <= RxData13;
						when 13  =>
						     Channel13 <= RxData14;
                        when 14  => 
							Channel14 <= RxData15;
						when 15  => 
							Channel15 <= RxData16;
                        when 16 => 
							Channel16 <= RxData17;
						when 17  =>
							Channel17 <= RxData18;
						when 18 =>
						    Channel18 <= RxData19;
                        when 19 => 
							Channel19 <= RxData20;
						when 20  => 
							Channel20 <= RxData21;
                        when 21 => 
							Channel21 <= RxData22;
						when 22  =>
							Channel22 <= RxData23;
						when 23  =>
						    Channel23 <= RxData24;
                        when 24  => 
							Channel24 <= RxData25;
						when 25  => 
							Channel25 <= RxData26;
                         when 26 => 
							Channel26 <= RxData27;
						when 27  =>
							Channel27 <= RxData28;
						when 28 =>
						    Channel28 <= RxData29;
                        when 29 => 
							Channel29 <= RxData30;
						when 30  => 
							Channel30 <= RxData31;
                        when 31 => 
							Channel31 <= RxData32;
						when 32  =>
							Channel32 <= RxData33;
						when 33  =>
						    Channel33 <= RxData34;
                        when 34  => 
							Channel34 <= RxData35;
						when 35  => 
							Channel35 <= RxData36;
					    when 36 => 
							Channel36 <= RxData37;
						when 37  =>
							Channel37 <= RxData38;
						when 38  =>
						    Channel38 <= RxData39;
                        when 39  => 
							Channel39 <= RxData40;
						when 40  => 
							Channel40 <= RxData41;
                        when 41 => 
							Channel41 <= RxData42;
						when 42  =>
							Channel42 <= RxData43;
						when 43 =>
						     Channel43 <= RxData44;
                        when 44 => 
							Channel44 <= RxData45;
						when 45  => 
							Channel45 <= RxData46;
                        when 46 => 
							Channel46 <= RxData47;
						when 47  =>
							Channel47 <= RxData48;
						when 48  =>
						     Channel48 <= RxData49;
                        when 49  => 
							Channel49 <= RxData50;
						when 50  => 
							Channel50 <= RxData51;
                        when 51 => 
							Channel51 <= RxData52;
						when 52  =>
							Channel52 <= RxData53;
						when 53 =>
						    Channel53 <= RxData54;
                        when 54 => 
							Channel54 <= RxData55;
						when 55  => 
							Channel55 <= RxData56;
                        when 56 => 
							Channel56 <= RxData57;
						when 57  =>
							Channel57 <= RxData58;
						when 58 =>
						    Channel58 <= RxData59;
                        when 59  => 
							Channel59 <= RxData60;
						when 60 => 
							Channel60 <= RxData61;
                         when 61 => 
							Channel61 <= RxData62;
						when 62  =>
							Channel62 <= RxData63;
						when 63 =>
						    Channel63 <= RxData64;
                        when 64 => 
							Channel64 <= RxData65;
						when 65  => 
							Channel65 <= RxData66;
                        when 66 => 
							Channel66 <= RxData67;
						when 67  =>
							Channel67 <= RxData68;
						when 68  =>
						    Channel68 <= RxData69;
                        when 69  => 
							Channel69 <= RxData70;
						when 70  => 
							Channel70 <= RxData71;
						when 71 => 
							Channel71 <= RxData72;
						when 72  =>
							Channel72 <= RxData73;
						when 73  =>
						    Channel73 <= RxData74;
                        when 74  => 
							Channel74 <= RxData75;
						when 75  => 
							Channel75 <= RxData76;
                        when 76 => 
							Channel76 <= RxData77;
						when 77 =>
							Channel77 <= RxData78;
						when 78 =>
						     Channel78 <= RxData79;
                        when 79 => 
							Channel79 <= RxData80;
						when 80  => 
							Channel80 <= RxData81;
                        when 81 => 
							Channel81 <= RxData82;
						when 82  =>
							Channel82 <= RxData83;
						when 83  =>
						     Channel83 <= RxData84;
                        when 84  => 
							Channel84 <= RxData85;
						when 85  => 
							Channel85 <= RxData86;
                        when 86 => 
							Channel86 <= RxData87;
						when 87  =>
							Channel87 <= RxData88;
						when 88 =>
						    Channel88 <= RxData89;
                        when 89 => 
							Channel89 <= RxData90;
						when 90  => 
							Channel90 <= RxData91;
                        when 91 => 
							Channel91 <= RxData92;
						when 92  =>
							Channel92 <= RxData93;
						when 93  =>
						    Channel93 <= RxData94;
                        when 94  => 
							Channel94 <= RxData95;
						when 95  => 
							Channel95 <= RxData96;
                         when 96 => 
							Channel96 <= RxData97;
						when 97  =>
							Channel97 <= RxData98;
						when 98 =>
						    Channel98 <= RxData99;
                        when 99 =>
						    Channel99 <= RxData100;
                        when others =>
							null;
					end case;
					if (BREAK = '1') then				-- Check for unexpected BREAK signal
						State <= WAITFORSTARTBYTE;		-- Abandon everything!
						ByteNumber := 0;
					end if;
				--======================================--						
			end case;
		end if; -- if reset = '0'...
		
--	Assigning all the channels
							Channel0 <= RxData1;
							
							Channel1 <= RxData2;
				
							Channel2 <= RxData3;
				
						    Channel3 <= RxData4;
                   
							Channel4 <= RxData5;
					
							Channel5 <= RxData6;
              
							Channel6 <= RxData7;
			
							Channel7 <= RxData8;
			
						    Channel8 <= RxData9;
              
							Channel9 <= RxData10;
			
							Channel10 <= RxData11;
       
							Channel11 <= RxData12;
			
							Channel12 <= RxData13;
				
						    Channel13 <= RxData14;
               
							Channel14 <= RxData15;

							Channel15 <= RxData16;
       
							Channel16 <= RxData17;
			
							Channel17 <= RxData18;
		
						    Channel18 <= RxData19;
       
							Channel19 <= RxData20;
		
							Channel20 <= RxData21;
    
							Channel21 <= RxData22;
	
							Channel22 <= RxData23;
	
						    Channel23 <= RxData24;
             
							Channel24 <= RxData25;
		
							Channel25 <= RxData26;
     
							Channel26 <= RxData27;
				
							Channel27 <= RxData28;
				
						    Channel28 <= RxData29;
                 
							Channel29 <= RxData30;
					
							Channel30 <= RxData31;
                 
							Channel31 <= RxData32;
					
							Channel32 <= RxData33;
			
						    Channel33 <= RxData34;
                  
							Channel34 <= RxData35;
					
							Channel35 <= RxData36;
				
							Channel36 <= RxData37;
					
							Channel37 <= RxData38;
					
						    Channel38 <= RxData39;
                     
							Channel39 <= RxData40;
					
							Channel40 <= RxData41;
                     
							Channel41 <= RxData42;
					
							Channel42 <= RxData43;
						
						    Channel43 <= RxData44;
                       
							Channel44 <= RxData45;
						
							Channel45 <= RxData46;
                      
							Channel46 <= RxData47;
						
							Channel47 <= RxData48;
						
						     Channel48 <= RxData49;
                      
							Channel49 <= RxData50;
						
							Channel50 <= RxData51;
                      
							Channel51 <= RxData52;
						
							Channel52 <= RxData53;
						
						    Channel53 <= RxData54;
                      
							Channel54 <= RxData55;
						 
							Channel55 <= RxData56;
                       
							Channel56 <= RxData57;
						
							Channel57 <= RxData58;
						
						    Channel58 <= RxData59;
                       
							Channel59 <= RxData60;
						 
							Channel60 <= RxData61;
                         
							Channel61 <= RxData62;
					
							Channel62 <= RxData63;
						
						    Channel63 <= RxData64;
                         
							Channel64 <= RxData65;
						
							Channel65 <= RxData66;
                      
							Channel66 <= RxData67;
						
							Channel67 <= RxData68;
						
						    Channel68 <= RxData69;
                     
							Channel69 <= RxData70;
				
							Channel70 <= RxData71;
					
							Channel71 <= RxData72;
					
							Channel72 <= RxData73;
					
						    Channel73 <= RxData74;
                       
							Channel74 <= RxData75;
						
							Channel75 <= RxData76;
                        
							Channel76 <= RxData77;
						
							Channel77 <= RxData78;
						
						    Channel78 <= RxData79;
                       
							Channel79 <= RxData80;
						 
							Channel80 <= RxData81;
                      
							Channel81 <= RxData82;
						
							Channel82 <= RxData83;
						
						    Channel83 <= RxData84;
                       
							Channel84 <= RxData85;
					 
							Channel85 <= RxData86;
                       
							Channel86 <= RxData87;
						
							Channel87 <= RxData88;
					
						    Channel88 <= RxData89;
                        
							Channel89 <= RxData90;
						 
							Channel90 <= RxData91;
                      
							Channel91 <= RxData92;
					
							Channel92 <= RxData93;
						
						    Channel93 <= RxData94;
                       
							Channel94 <= RxData95;
					
							Channel95 <= RxData96;
                         
							Channel99 <= RxData97;
						
							Channel97 <= RxData98;
						
						    Channel98 <= RxData99;
                        
						    Channel99 <= RxData100;
						       
	end process;
			

end uart; --===================== End of architecture =======================--
-------------------------------------------------------------------------------
-- Entity for Receive Unit - 250K DMX baudrate                               --
-------------------------------------------------------------------------------
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
--library work;
--   use work.UART_Def.all;
-------------------------------------------------------------------------------
-- Receive unit
-------------------------------------------------------------------------------
entity RxUnit is
  port (
     Clk           : in  Std_Logic;  -- system clock signal
     Reset         : in  Std_Logic;  -- Reset input
     RxD           : in  Std_Logic;  -- RS-232 data input
     BREAK         : out Std_Logic;  -- Status signal
     DataIn1       : out Std_Logic_Vector(7 downto 0);
     DataIn2       : out Std_Logic_Vector(7 downto 0);
     DataIn3       : out Std_Logic_Vector(7 downto 0);
     DataIn4       : out Std_Logic_Vector(7 downto 0);
     DataIn5       : out Std_Logic_Vector(7 downto 0);
     DataIn6       : out Std_Logic_Vector(7 downto 0);
     DataIn7       : out Std_Logic_Vector(7 downto 0);
     DataIn8       : out Std_Logic_Vector(7 downto 0);
     DataIn9       : out Std_Logic_Vector(7 downto 0);
     DataIn10      : out Std_Logic_Vector(7 downto 0);
     DataIn11      : out Std_Logic_Vector(7 downto 0);
     DataIn12      : out Std_Logic_Vector(7 downto 0);
     DataIn13      : out Std_Logic_Vector(7 downto 0);
     DataIn14      : out Std_Logic_Vector(7 downto 0);
     DataIn15      : out Std_Logic_Vector(7 downto 0);
     DataIn16      : out Std_Logic_Vector(7 downto 0);
     DataIn17      : out Std_Logic_Vector(7 downto 0);
     DataIn18      : out Std_Logic_Vector(7 downto 0);
     DataIn19      : out Std_Logic_Vector(7 downto 0);
     DataIn20      : out Std_Logic_Vector(7 downto 0);
     DataIn21      : out Std_Logic_Vector(7 downto 0);
     DataIn22      : out Std_Logic_Vector(7 downto 0);
     DataIn23      : out Std_Logic_Vector(7 downto 0);
     DataIn24      : out Std_Logic_Vector(7 downto 0);
     DataIn25      : out Std_Logic_Vector(7 downto 0);
     DataIn26      : out Std_Logic_Vector(7 downto 0);
     DataIn27      : out Std_Logic_Vector(7 downto 0);
     DataIn28      : out Std_Logic_Vector(7 downto 0);
     DataIn29      : out Std_Logic_Vector(7 downto 0);
     DataIn30      : out Std_Logic_Vector(7 downto 0);
     DataIn31      : out Std_Logic_Vector(7 downto 0);
     DataIn32      : out Std_Logic_Vector(7 downto 0);
     DataIn33      : out Std_Logic_Vector(7 downto 0);
     DataIn34      : out Std_Logic_Vector(7 downto 0);
     DataIn35      : out Std_Logic_Vector(7 downto 0);
     DataIn36      : out Std_Logic_Vector(7 downto 0);
     DataIn37      : out Std_Logic_Vector(7 downto 0);
     DataIn38      : out Std_Logic_Vector(7 downto 0);
     DataIn39      : out Std_Logic_Vector(7 downto 0);
     DataIn40      : out Std_Logic_Vector(7 downto 0);
     DataIn41      : out Std_Logic_Vector(7 downto 0);
     DataIn42      : out Std_Logic_Vector(7 downto 0);
     DataIn43      : out Std_Logic_Vector(7 downto 0);
     DataIn44      : out Std_Logic_Vector(7 downto 0);
     DataIn45      : out Std_Logic_Vector(7 downto 0);
     DataIn46      : out Std_Logic_Vector(7 downto 0);
     DataIn47      : out Std_Logic_Vector(7 downto 0);
     DataIn48      : out Std_Logic_Vector(7 downto 0);
     DataIn49      : out Std_Logic_Vector(7 downto 0);
     DataIn50      : out Std_Logic_Vector(7 downto 0);
     DataIn51      : out Std_Logic_Vector(7 downto 0);
     DataIn52      : out Std_Logic_Vector(7 downto 0);
     DataIn53      : out Std_Logic_Vector(7 downto 0);
     DataIn54      : out Std_Logic_Vector(7 downto 0);
     DataIn55      : out Std_Logic_Vector(7 downto 0);
     DataIn56      : out Std_Logic_Vector(7 downto 0);
     DataIn57      : out Std_Logic_Vector(7 downto 0);
     DataIn58      : out Std_Logic_Vector(7 downto 0);
     DataIn59      : out Std_Logic_Vector(7 downto 0);
     DataIn60      : out Std_Logic_Vector(7 downto 0);
     DataIn61      : out Std_Logic_Vector(7 downto 0);
     DataIn62      : out Std_Logic_Vector(7 downto 0);
     DataIn63      : out Std_Logic_Vector(7 downto 0);
     DataIn64      : out Std_Logic_Vector(7 downto 0);
     DataIn65      : out Std_Logic_Vector(7 downto 0);
     DataIn66      : out Std_Logic_Vector(7 downto 0);
     DataIn67      : out Std_Logic_Vector(7 downto 0);
     DataIn68      : out Std_Logic_Vector(7 downto 0);
     DataIn69      : out Std_Logic_Vector(7 downto 0);
     DataIn70      : out Std_Logic_Vector(7 downto 0);
     DataIn71      : out Std_Logic_Vector(7 downto 0);
     DataIn72      : out Std_Logic_Vector(7 downto 0);
     DataIn73      : out Std_Logic_Vector(7 downto 0);
     DataIn74      : out Std_Logic_Vector(7 downto 0);
     DataIn75      : out Std_Logic_Vector(7 downto 0);
     DataIn76      : out Std_Logic_Vector(7 downto 0);
     DataIn77      : out Std_Logic_Vector(7 downto 0);
     DataIn78      : out Std_Logic_Vector(7 downto 0);
     DataIn79      : out Std_Logic_Vector(7 downto 0);
     DataIn80      : out Std_Logic_Vector(7 downto 0);
     DataIn81      : out Std_Logic_Vector(7 downto 0);
     DataIn82      : out Std_Logic_Vector(7 downto 0);
     DataIn83      : out Std_Logic_Vector(7 downto 0);
     DataIn84      : out Std_Logic_Vector(7 downto 0);
     DataIn85      : out Std_Logic_Vector(7 downto 0);
     DataIn86      : out Std_Logic_Vector(7 downto 0);
     DataIn87      : out Std_Logic_Vector(7 downto 0);
     DataIn88      : out Std_Logic_Vector(7 downto 0);
     DataIn89      : out Std_Logic_Vector(7 downto 0);
     DataIn90      : out Std_Logic_Vector(7 downto 0);
     DataIn91      : out Std_Logic_Vector(7 downto 0);
     DataIn92      : out Std_Logic_Vector(7 downto 0);
     DataIn93      : out Std_Logic_Vector(7 downto 0);
     DataIn94      : out Std_Logic_Vector(7 downto 0);
     DataIn95      : out Std_Logic_Vector(7 downto 0);
     DataIn96      : out Std_Logic_Vector(7 downto 0);
     DataIn97      : out Std_Logic_Vector(7 downto 0);
     DataIn98      : out Std_Logic_Vector(7 downto 0);
     DataIn99      : out Std_Logic_Vector(7 downto 0);
     DataIn100     : out Std_Logic_Vector(7 downto 0);
	 BitStart      : out Std_Logic);
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for receive Unit
-------------------------------------------------------------------------------
architecture Behaviour of RxUnit is
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
  signal Start     		: Std_Logic;             -- Syncro signal
  signal tmpRxD    		: Std_Logic;             -- RxD buffer
  signal BreakDetected  : Std_Logic;             -- 
  signal BitCnt    		: Unsigned(3 downto 0);  -- 
  signal SampleCnt 		: Unsigned(3 downto 0);  -- samples on one bit counter
  signal ShtReg    		: Std_Logic_Vector(7 downto 0);  --
  signal DOut1      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut2      	: Std_Logic_Vector(7 downto 0);  
  signal DOut3      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut4      	: Std_Logic_Vector(7 downto 0);  
  signal DOut5      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut6     		: Std_Logic_Vector(7 downto 0);  
  signal DOut7      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut8     		: Std_Logic_Vector(7 downto 0);  
  signal DOut9      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut10      	: Std_Logic_Vector(7 downto 0);  
  signal DOut11      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut12      	: Std_Logic_Vector(7 downto 0);  
  signal DOut13      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut14      	: Std_Logic_Vector(7 downto 0);  
  signal DOut15      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut16     	: Std_Logic_Vector(7 downto 0);  
  signal DOut17      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut18      	: Std_Logic_Vector(7 downto 0);  
  signal DOut19      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut20      	: Std_Logic_Vector(7 downto 0);  
  signal DOut21      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut22     	: Std_Logic_Vector(7 downto 0);  
  signal DOut23      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut24      	: Std_Logic_Vector(7 downto 0); 
  signal DOut25      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut26      	: Std_Logic_Vector(7 downto 0);  
  signal DOut27      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut28      	: Std_Logic_Vector(7 downto 0);  
  signal DOut29      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut30      	: Std_Logic_Vector(7 downto 0);  
  signal DOut31      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut32      	: Std_Logic_Vector(7 downto 0);  
  signal DOut33      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut34      	: Std_Logic_Vector(7 downto 0);  
  signal DOut35      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut36      	: Std_Logic_Vector(7 downto 0); 
  signal DOut37      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut38     	: Std_Logic_Vector(7 downto 0);  
  signal DOut39      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut40      	: Std_Logic_Vector(7 downto 0);  
  signal DOut41      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut42    		: Std_Logic_Vector(7 downto 0);  
  signal DOut43     	: Std_Logic_Vector(7 downto 0);  --
  signal DOut44    		: Std_Logic_Vector(7 downto 0);  
  signal DOut45     	: Std_Logic_Vector(7 downto 0);  --
  signal DOut46      	: Std_Logic_Vector(7 downto 0);  
  signal DOut47      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut48      	: Std_Logic_Vector(7 downto 0);  
  signal DOut49      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut50      	: Std_Logic_Vector(7 downto 0);  
  signal DOut51      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut52     	: Std_Logic_Vector(7 downto 0);  
  signal DOut53      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut54      	: Std_Logic_Vector(7 downto 0);  
  signal DOut55      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut56      	: Std_Logic_Vector(7 downto 0);  
  signal DOut57      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut58     	: Std_Logic_Vector(7 downto 0);  
  signal DOut59      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut60      	: Std_Logic_Vector(7 downto 0); 
  signal DOut61      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut62      	: Std_Logic_Vector(7 downto 0);  
  signal DOut63      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut64      	: Std_Logic_Vector(7 downto 0);  
  signal DOut65      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut66      	: Std_Logic_Vector(7 downto 0);  
  signal DOut67      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut68      	: Std_Logic_Vector(7 downto 0);  
  signal DOut69      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut70      	: Std_Logic_Vector(7 downto 0);  
  signal DOut71      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut72      	: Std_Logic_Vector(7 downto 0); 
  signal DOut73     	: Std_Logic_Vector(7 downto 0);  --
  signal DOut74     	: Std_Logic_Vector(7 downto 0);  
  signal DOut75     	: Std_Logic_Vector(7 downto 0);  --
  signal DOut76     	: Std_Logic_Vector(7 downto 0);  
  signal DOut77     	: Std_Logic_Vector(7 downto 0);  --
  signal DOut78    		: Std_Logic_Vector(7 downto 0);  
  signal DOut79     	: Std_Logic_Vector(7 downto 0);  --
  signal DOut80     	: Std_Logic_Vector(7 downto 0);  
  signal DOut81     	: Std_Logic_Vector(7 downto 0);  --
  signal DOut82      	: Std_Logic_Vector(7 downto 0);  
  signal DOut83      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut84      	: Std_Logic_Vector(7 downto 0);  
  signal DOut85      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut86      	: Std_Logic_Vector(7 downto 0);  
  signal DOut87      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut88     	: Std_Logic_Vector(7 downto 0);  
  signal DOut89      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut90      	: Std_Logic_Vector(7 downto 0);  
  signal DOut91      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut92      	: Std_Logic_Vector(7 downto 0);  
  signal DOut93      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut94     	: Std_Logic_Vector(7 downto 0);  
  signal DOut95      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut96      	: Std_Logic_Vector(7 downto 0); 
  signal DOut97      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut98      	: Std_Logic_Vector(7 downto 0);  
  signal DOut99      	: Std_Logic_Vector(7 downto 0);  --
  signal DOut100      	: Std_Logic_Vector(7 downto 0);   
begin
  ---------------------------------------------------------------------
  -- Receiver process
  ---------------------------------------------------------------------
  RcvProc : process(Clk,Reset,RxD)
      variable tmpBitCnt    : Integer range 0 to 15;
      variable tmpSampleCnt : Integer range 0 to 15;
      constant CntOne       : Unsigned(3 downto 0):="0001";
  begin
     if Rising_Edge(Clk) then
        --tmpBitCnt := ToInteger(BitCnt);
		tmpBitCnt := To_Integer(BitCnt);
        --tmpSampleCnt := ToInteger(SampleCnt);
        tmpSampleCnt := To_Integer(SampleCnt);
        if Reset = '0' then
           BitCnt <= "0000";
           SampleCnt <= "0000";
		   Start <= '0';
           BreakDetected <= '0';
           ShtReg <= "00000000";  --
          
     DOut1  <=  "00000000";
     DOut2  <= "00000101";
     DOut3  <= "00000111";
     DOut4  <= "00001001";
     DOut5  <= "00001110";
     DOut6  <= "00010001";
     DOut7  <= "00010011";
     DOut8  <= "00010111";
     DOut9  <= "00011001";
     DOut10 <= "00101000";
     DOut11 <= "00101101";
     DOut12 <= "00110001";
     DOut13 <= "00110100";
     DOut14 <= "00110111";
     DOut15 <= "00111111";
     DOut16 <= "01000011";
     DOut17 <= "01000100";
     DOut18 <= "01010100";
     DOut19 <= "01010101";
     DOut20 <= "01011001";
     DOut21 <= "01101001";
     DOut22 <= "01101101";
     DOut23 <= "01110000";
     DOut24 <= "01110101";
     DOut25 <= "01111110";
     DOut26 <= "01101101";
     DOut27 <= "01110110";
     DOut28 <= "01111011";
     DOut29 <= "01000001";
     DOut30 <= "10000100";
     DOut31 <= "10001010";
     DOut32 <= "10001101";
     DOut33 <= "10010010";
     DOut34 <= "11111001";
     DOut35 <= "11111101";
     DOut36 <= "11111111";
     DOut37 <= "10011101";
     DOut38 <= "10100010";
     DOut39 <= "10101101";
     DOut40 <= "10110011";
     DOut41 <= "10110110";
     DOut42 <= "10111101";
     DOut43 <= "10111111";
     DOut44 <= "11001100";
     DOut45 <= "11010001";
     DOut46 <= "11010011";
     DOut47 <= "11011010";
     DOut48 <= "11011011";
     DOut49 <= "11011110";
     DOut50 <= "11100101";
     DOut51 <= "11111111";
     DOut52 <= "11101000";
     DOut53 <= "11101100";
     DOut54 <= "11101111";
     DOut55 <= "11110001";
     DOut56 <= "11110011";
     DOut57 <= "11110111";
     DOut58 <= "11111001";
     DOut59 <= "11111011";
     DOut60 <= "11010010";
     DOut61 <= "11011001";
     DOut62 <= "11101010";
     DOut63 <= "11100010";
     DOut64 <= "11110000";
     DOut65 <= "11110110";
     DOut66 <= "11111000";
     DOut67 <= "11111100";
     DOut68 <= "10101110";
     DOut69 <= "10110000";
     DOut70 <= "10100000";
     DOut71 <= "10011010";
     DOut72 <= "10011100";
     DOut73 <= "10011001";
     DOut74 <= "10001111";
     DOut75 <= "01100011";
     DOut76 <= "10000000";
     DOut77 <= "10001001";
     DOut78 <= "10010100";
     DOut79 <= "00110110";
     DOut80 <= "00111101";
     DOut81 <= "00010100";
     DOut82 <= "00011010";
     DOut83 <= "00010011";
     DOut84 <= "10001011";
     DOut85 <= "10010000";
     DOut86 <= "01010001";
     DOut87 <= "01011011";
     DOut88 <= "01100000";
     DOut89 <= "01111101";
     DOut90 <= "10001000";
     DOut91 <= "10000010";
     DOut92 <= "01111000";
     DOut93 <= "01101110";
     DOut94 <= "10111001";
     DOut95 <= "11000100";
     DOut96 <= "01100100";
     DOut97 <= "01111010";
     DOut98 <= "11011000";
     DOut99 <= "01101111";
     DOut100 <= "11100110";
        else
          if Start = '0' then
             if RxD = '0' then -- Start bit, 
                SampleCnt <= SampleCnt + CntOne;
                Start <= '1';
				BreakDetected <= '0';	-- clear output
             end if;
          else
             if tmpSampleCnt = 8 then  -- reads the RxD line
                tmpRxD <= RxD;
                --BitStart <= '1';	-- position marker for debugging
				SampleCnt <= SampleCnt + CntOne;                
             elsif tmpSampleCnt = 15 then 
				--BitStart <= '0';	-- position marker for debugging
				
	 case tmpBitCnt is
                    
                     when 0 => -- Waiting for start bit (should be '0')
                            if tmpRxD = '1' then -- Not detected.
                               Start <= '0';
							   --tmpDRdy <= '0';
                            else
                                BitCnt <= BitCnt + CntOne;
                            end if;
                            SampleCnt <= SampleCnt + CntOne;
                     when 1|2|3|4|5|6|7|8 =>
                            BitCnt <= BitCnt + CntOne;
                            SampleCnt <= SampleCnt + CntOne;
                            ShtReg <= tmpRxD & ShtReg(7 downto 1);
                     when 9 => --1st stop bit
                            if tmpRxD = '0' then  -- Check for stop bit (should be '1')
							-- Stop bit not detected.  Either fault, or BREAK signal.
           	                	BreakDetected <= '1';
    	                        BitCnt <= BitCnt + CntOne; -- Goto state 10 and wait for stop
	                            SampleCnt <= SampleCnt + CntOne;
                            else
                              	-- Stop bit found so reset and wait for
								-- next falling edge of start bit.
								BreakDetected <= '0';
							   	BitCnt <= "0000"; -- Goto state 00 and wait for start
							    SampleCnt <= "0000";
				                Start <= '0';
                            end if;

							DOut1 <= ShtReg;
							DOut2 <= ShtReg;
                            DOut3 <= ShtReg;
							DOut4 <= ShtReg;
                            DOut5 <= ShtReg;
							DOut6 <= ShtReg;
                            DOut7 <= ShtReg;
							DOut8 <= ShtReg;
                            DOut9 <= ShtReg;
							DOut10 <= ShtReg;
                            DOut11 <= ShtReg;
							DOut12 <= ShtReg;
                            DOut13 <= ShtReg;
							DOut14 <= ShtReg;
                            DOut15 <= ShtReg;
							DOut16 <= ShtReg;
                            DOut17 <= ShtReg;
							DOut18 <= ShtReg;
                            DOut19 <= ShtReg;
							DOut20 <= ShtReg;
                            DOut21 <= ShtReg;
							DOut22 <= ShtReg;
                            DOut23 <= ShtReg;
							DOut24 <= ShtReg;
                            DOut25 <= ShtReg;
							DOut26 <= ShtReg;
                            DOut27 <= ShtReg;
							DOut28 <= ShtReg;
                            DOut29 <= ShtReg;
							DOut30 <= ShtReg;
                            DOut31 <= ShtReg;
							DOut32 <= ShtReg;
                            DOut33 <= ShtReg;
							DOut34 <= ShtReg;
                            DOut35 <= ShtReg;
							DOut36 <= ShtReg;
							DOut37 <= ShtReg;
							DOut38 <= ShtReg;
                            DOut39 <= ShtReg;
							DOut40 <= ShtReg;
                            DOut41 <= ShtReg;
							DOut42 <= ShtReg;
                            DOut43 <= ShtReg;
							DOut44 <= ShtReg;
                            DOut45 <= ShtReg;
							DOut46 <= ShtReg;
                            DOut47 <= ShtReg;
							DOut48 <= ShtReg;
                            DOut49 <= ShtReg;
							DOut50 <= ShtReg;
                            DOut51 <= ShtReg;
							DOut52 <= ShtReg;
                            DOut53 <= ShtReg;
							DOut54 <= ShtReg;
                            DOut55 <= ShtReg;
							DOut56 <= ShtReg;
                            DOut57 <= ShtReg;
							DOut58 <= ShtReg;
                            DOut59 <= ShtReg;
							DOut60 <= ShtReg;
                            DOut61 <= ShtReg;
							DOut62 <= ShtReg;
                            DOut63 <= ShtReg;
							DOut64 <= ShtReg;
                            DOut65 <= ShtReg;
							DOut66 <= ShtReg;
                            DOut67 <= ShtReg;
							DOut68 <= ShtReg;
                            DOut69 <= ShtReg;
							DOut70 <= ShtReg;
                            DOut71 <= ShtReg;
							DOut72 <= ShtReg;
							DOut73 <= ShtReg;
							DOut74 <= ShtReg;
                            DOut75 <= ShtReg;
							DOut76 <= ShtReg;
                            DOut77 <= ShtReg;
							DOut78 <= ShtReg;
                            DOut79 <= ShtReg;
							DOut80 <= ShtReg;
                            DOut81 <= ShtReg;
							DOut82 <= ShtReg;
                            DOut83 <= ShtReg;
							DOut84 <= ShtReg;
                            DOut85 <= ShtReg;
							DOut86 <= ShtReg;
                            DOut87 <= ShtReg;
							DOut88 <= ShtReg;
                            DOut89 <= ShtReg;
							DOut90 <= ShtReg;
                            DOut91 <= ShtReg;
							DOut92 <= ShtReg;
                            DOut93 <= ShtReg;
							DOut94 <= ShtReg;
                            DOut95 <= ShtReg;
							DOut96 <= ShtReg;
                            DOut97 <= ShtReg;
							DOut98 <= ShtReg;
                            DOut99 <= ShtReg;
							DOut100 <= ShtReg;
                            
                                                                                                           
					 when 10 => 
							-- Ensure RxD is high before continuing...
							-- This caters for BREAK byte length (88uS with no stop bits)
							if BreakDetected = '1' then -- we are waiting for a return to a high state
								if tmpRxD = '1' then 	-- check for high state
						   			-- High state detected, so abandon this and wait for the falling
									-- edge of the next START bit.
		                        	BitCnt <= "0000";	
									SampleCnt <= "0000";
					                Start <= '0';
								end if;
							SampleCnt <= SampleCnt + CntOne;
							end if;
						
                     when others =>
                          null;
                end case;
			
             else
                SampleCnt <= SampleCnt + CntOne;                
             end if;
          end if;
	   end if; -- if reset...
	end if; -- rising clock
  end process;

	DataIn1 <= DOut1;
	DataIn2 <= DOut2;
    DataIn3 <= DOut3;
	DataIn4 <= DOut4;
    DataIn5 <= DOut5;
	DataIn6 <= DOut6;
    DataIn7 <= DOut7;
	DataIn8 <= DOut8;
    DataIn9 <= DOut9;
	DataIn10 <= DOut10;
    DataIn11 <= DOut11;
	DataIn12 <= DOut12;
    DataIn13 <= DOut13;
	DataIn14 <= DOut14;
    DataIn15 <= DOut15;
	DataIn16 <= DOut16; 
    DataIn17 <= DOut17;
	DataIn18 <= DOut18;
    DataIn19 <= DOut19;
	DataIn20 <= DOut20;
    DataIn21 <= DOut21;
	DataIn22 <= DOut22;
    DataIn23 <= DOut23;
	DataIn24 <= DOut24;
    DataIn25 <= DOut25;
	DataIn26 <= DOut26;
    DataIn27 <= DOut27;
	DataIn28 <= DOut28;
    DataIn29 <= DOut29;
	DataIn30 <= DOut30;
    DataIn31 <= DOut31;
	DataIn32 <= DOut32;
    DataIn33 <= DOut33;
	DataIn34 <= DOut34;
    DataIn35 <= DOut35;
	DataIn36 <= DOut36;
	DataIn37 <= DOut37;
	DataIn38 <= DOut38;
    DataIn39 <= DOut39;
	DataIn40 <= DOut40;
    DataIn41 <= DOut41;
	DataIn42 <= DOut42;
    DataIn43 <= DOut43;
	DataIn44 <= DOut44;
    DataIn45 <= DOut45;
	DataIn46 <= DOut46;
    DataIn47 <= DOut47;
	DataIn48 <= DOut48;
    DataIn49 <= DOut49;
	DataIn50 <= DOut50;
    DataIn51 <= DOut51;
	DataIn52 <= DOut52; 
    DataIn53 <= DOut53;
	DataIn54 <= DOut54;
    DataIn55 <= DOut55;
	DataIn56 <= DOut56;
    DataIn57 <= DOut57;
	DataIn58 <= DOut58;
    DataIn59 <= DOut59;
	DataIn60 <= DOut60;
    DataIn61 <= DOut61;
	DataIn62 <= DOut62;
    DataIn63 <= DOut63;
	DataIn64 <= DOut64;
    DataIn65 <= DOut65;
	DataIn66 <= DOut66;
    DataIn67 <= DOut67;
	DataIn68 <= DOut68;
    DataIn69 <= DOut69;
	DataIn70 <= DOut70;
    DataIn71 <= DOut71;
	DataIn72 <= DOut72;
	DataIn73 <= DOut73;
	DataIn74 <= DOut74;
    DataIn75 <= DOut75;
	DataIn76 <= DOut76;
    DataIn77 <= DOut77;
	DataIn78 <= DOut78;
    DataIn79 <= DOut79;
	DataIn80 <= DOut80;
    DataIn81 <= DOut81;
	DataIn82 <= DOut82;
    DataIn83 <= DOut83;
	DataIn84 <= DOut84;
    DataIn85 <= DOut85;
	DataIn86 <= DOut86;
    DataIn87 <= DOut87;
	DataIn88 <= DOut88; 
    DataIn89 <= DOut89;
	DataIn90 <= DOut90;
    DataIn91 <= DOut91;
	DataIn92 <= DOut92;
    DataIn93 <= DOut93;
	DataIn94 <= DOut94;
    DataIn95 <= DOut95;
	DataIn96 <= DOut96;
    DataIn97 <= DOut97;
	DataIn98 <= DOut98;
    DataIn99 <= DOut99;
	DataIn100 <= DOut100;
                
	BREAK <= BreakDetected;
	BitStart <= Start;
	
end Behaviour;